1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to a self-aligned double patterning process for two dimensional patterns.
2. Description of the Related Art
Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves: (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate; (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material; and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength immersion photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as multiple patterning, e.g., double patterning. In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively lowers the complexity of the photolithography process, improving the achievable resolution and enabling the printing of far smaller features that would otherwise be impossible using existing photolithography tools. The self-aligned double patterning (SADP) process is one such multiple patterning technique. The SADP process may be an attractive solution for manufacturing next-generation devices, particularly metal routing lines on such next-generation devices, due to better overlay control that is possible when using an SADP process.
FIG. 1A illustrates a design layout for an exemplary interconnect structure 100. The interconnect structure 100 includes conductive elements, such as metal lines, embedded in a dielectric layer. The illustrated interconnect structure 100 is useful for implementing logic standard cells, which interconnect transistors (e.g., CMOS devices) to provide a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flip-flop or latch). The interconnect structure 100 includes a horizontal conductive line 105, which may be used as a power rail in a standard logic cell array, and a series of vertical conductive lines 110, which may be used for inter-cell connections to define the logic elements. A gate layer (e.g., polysilicon) (not shown) may be formed beneath the interconnect structure 100 to define the actual logic operations for the cells.
To form the ultra-regular, dense interconnect structure 100 of FIG. 1A, which is preferred for 10 nm technology or smaller due to the complexity of manufacturing conventionally 2D (two dimensional) interconnect patterns, an SADP process is conventionally used to minimize the alignment error between two adjacent lines. FIG. 1B illustrates one illustrative SADP template 150 for forming the interconnect structure 100. The polygons with dotted shading and dashed lines reflect the desired pattern of the interconnect structure 100. The template includes mandrel elements 155. FIG. 1C illustrates the SADP template 150 after a spacer layer (not shown) was formed above the mandrel elements 155, the spacer layer was etched to define spacers 160 adjacent the mandrel elements 155, and the mandrel elements 155 were removed. The spacers 160 define an etch mask for the vertical lines 110. FIG. 1D illustrates the SADP template 150 after block masks 165, 170 (e.g., photoresist) are formed to define the pattern for the horizontal line 105. The template 150 illustrated in FIG. 1D may be used to etch an underlying hard mask layer, and, subsequently, a dielectric layer beneath the hard mask layer may be etched to define trench recesses. The trench recesses may be filled with metal to complete the interconnect structure 100 illustrated in FIG. 1B.
The patterning process illustrated in FIGS. 1A-1D has several limitations. FIG. 1E illustrates the template 150 showing the mandrel elements 155 and the block masks 165, 170 to illustrate these limitations. The mandrel elements 155 define a 2D pattern due to the line ends, i.e., a pattern that does not exhibit spacing constraints in just one direction. The tip-to-tip spacing 175 between the mandrel elements 155 is limited by the photolithography process. For example, assuming a minimum dimension of the block masks 165, 170 being 40 nm and a minimum space between the block masks 165, 170 being 40 nm, the minimum tip-to-tip spacing 175 is 120 nm. Also, when printing the mandrel elements 155, non-ideal printing that occurs in a normal photolithography process results in corner rounding (not shown) and pull-back (not shown) in the line ends, further increasing the tip-to-tip spacing 175 and increasing the difficulties associated with forming vias (not shown) above the interconnect structure 100 to contact the lines 110.
FIG. 1F illustrates another approach to forming the interconnect structure 100 by employing a triple patterning process. For each patterning step, there are photolithography and etching steps. A first set of vertical lines 110A is formed with a first patterning step, a second set of vertical lines 110B (i.e., interleaved with respect to the first set) is formed with a second patterning step, and the horizontal line 105C is formed with a third patterning step. The sets of vertical lines 110A, 110B are interleaved to address minimum spacing constraints. This approach suffers from line-to-line misalignment issues and poor line end printability due to pull-back and corner rounding.
The present disclosure is directed to various methods for forming 2D patterns using a 1D self-aligned double patterning process to manufacture integrated circuit products which may solve or at least reduce one or more of the problems identified above.